PCB Stack
Four-layer LED driver, pulled apart. Conventional current leaves the 5 V pin, goes through the load, and comes back on the ground plane under the trace.
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4-layer · 1.60 mm
Drag to orbit. Pinch or scroll to zoom. Tap a trace.
Thin layers exaggerated
J1
U1
C1 C2
330
R1
D1
No net selected
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Tap a trace, via, plane, or a net below.
Width
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Path length
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R at 20 °C
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α
0.00393 /°C
IR drop
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IPC-2221 ΔT
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Stack
4-layer
2-layer
Collapsed
Exploded
Fit view
Current
15 mA
1 A
Layers
All
Copper
R = ρ L / (w t) for 1 oz copper. ρ = 1.7241×10⁻⁸ Ω·m at 20 °C (100% IACS), t = 1.378 mil, α = 0.00393 /°C. Via barrels use the plated annulus, π · t · (drill − t), 25 µm plating. IPC-2221 estimate: I = k ΔT^0.44 A^0.725, A in mil², k = 0.048 on outer layers and 0.024 inside. It is a chart fit and it runs hot compared with IPC-2152. The power path on 4 layers is a 1.5 mm strip between stitch vias. The ground return is the solid plane: sheet resistance, spread across the trace plus 3 dielectric heights either side. That is an estimate, and IPC-2221 is not applied to the pour. XY is true millimeters. Real stack is 1.60 mm, and 1 oz copper is 35 µm. The picture exaggerates the thin films more than the core so the copper sheets show, and the core stays the thick layer. The explode gap is only in the picture. Particles show direction and the current setting. They are not drift speed. Collapse keeps the top-side dots on the mask; explode them to see the return on the ground plane. Traces are drawn at least 0.9 mm wide so the route reads. The readout is the real width. Signal barrels are drawn about 0.8 mm across so the plating reads; the resistance still uses the real drill and 25 µm plate.